Kazuo Sakiyama, Patrick Schaumont, and Ingrid Verbauwhede, “Design Methods for Secure Hardware,” NII Shonan Meeting (Sep. 15–19, 2014).
Kazuo Sakiyama, “Fault Analysis for Cryptosystems: Introduction to Differential Fault Analysis and Fault Sensitivity Analysis,” Tutorial-4: Hardware Trust in VLSI Design and Implementations, Asia and South Pacific Design Automation Conference (ASP-DAC’15), Tutorial Session (Jan., 2015).
Kazuo Sakiyama, Lejla Batina, Bart Preneel, and Ingrid Verbauwhede, “HW/SW Co-design for Accelerating Public-Key Cryptosystems over GF(p) on the 8051 μ-controller,” In Proc. World Automation Congress (WAC’06), 6 pages (Jul., 2006).
Nele Mentens, Kazuo Sakiyama, Lejla Batina, Ingrid Verbauwhede, and Bart Preneel, “FPGA-Oriented Secure Data Path Design: Implementation of a Public Key Coprocessor,” In Proc. 16th International Conference on Field Programmable Logic and Applications (FPL’06), IEEE, pp.133–138 (Aug., 2006).
Lejla Batina, Alireza Hodjat, David Hwang, Kazuo Sakiyama, and Ingrid Verbauwhede, “Reconfigurable Architectures for Curve-Based Cryptography on Embedded Micro-controllers,” In Proc. 16th International Conference on Field Programmable Logic and Applications (FPL’06), IEEE, pp.667–670 (Aug., 2006).
Lejla Batina, Nele Mentens, Kazuo Sakiyama, Bart Preneel, and Ingrid Verbauwhede, “Low-Cost Elliptic Curve Cryptography for Wireless Sensor Networks,” In Third European Workshop on Security and Privacy in Ad Hoc and Sensor Networks (ESAS’06), LNCS 4357, Springer-Verlag, pp.6-17 (Sep., 2006).
Kazuo Sakiyama, Lejla Batina, Bart Preneel, and Ingrid Verbauwhede, “Superscalar Coprocessor for High-Speed Curve-Based Cryptography,” In Workshop on Cryptographic Hardware and Embedded Systems (CHES’06), LNCS 4249, Springer-Verlag, pp.415–429 (Oct., 2006).
Nele Mentens, Kazuo Sakiyama, Bart Preneel, and Ingrid Verbauwhede, “Efficient Pipelining for Modular Multiplication Architectures in Prime Fields,” In Proc. 2007 Great Lakes Symposium on VLSI (GLSVLSI’07), ACM, pp.534–539 (Mar., 2007).
Kazuo Sakiyama, Elke De Mulder, Bart Preneel, and Ingrid Verbauwhede, “Side-channel Resistant System-level Design Flow for Public-key Cryptography,” In Proc. 2007 Great Lakes Symposium on VLSI (GLSVLSI’07), ACM, pp.144–147 (Mar., 2007).
