アーカイブ

Takeshi Sugawara, Kazuo Sakiyama, Shoei Nashimoto, Daisuke Suzuki, and Tomoyuki Nagatsuka, “Oscillator without a Combinatorial Loop and its Threat to FPGA in Data Center,” IET Electronics Letters, Vol.55, Issue 11, pp.640–642 (May, 2019).

Takeshi Sugawara, Natsu Shoji, Kazuo Sakiyama, Kohei Matsuda, Noriyuki Miura, and Makoto Nagata, “Side-Channel Leakage from Sensor-Based Countermeasures against Fault Injection Attack,” Microelectronics Journal, Vol.90, pp.63–71 (Aug., 2019).

Akiko Toh, Yang Li, Kazuo Sakiyama, and Takeshi Sugawara, “Fingerprinting Light Emitting Diodes Using Spectrometer,” IET Electronics Letters, Vol.55, Issue 24, pp.1295–1297 (Nov., 2019).

Kohei Matsuda, Sho Tada, Makoto Nagata, Yuichi Komano, Yang Li, Takeshi Sugawara, Mitsugu Iwamoto, Kazuo Ohta, Kazuo Sakiyama, and Noriyuki Miura, “An IC-level countermeasure against laser fault injection attack by information leakage sensing based on laser-induced opto-electric bulk current density,” J. Appl. Phys. 59, SGGL02, 12pages (Feb., 2020).

八代理紗, 堀洋平, 片下敏宏, 崎山一男, “意図的なエラーを付与することによる深層学習を用いたArbiter PUFへのクローニング攻撃の対策,” 情報処理学会論文誌, Vol.61, No.12, pp.1871–1880 (Dec., 2020).

羽田野凌太, 平田 遼, 松田航平, 三浦典之, 李陽, 崎山一男, “LFI検知回路に対するサイドチャネル攻撃耐性評価,” 電子情報通信学会論文誌(A), Vol.J104-A, No.5, pp.118–126 (May., 2021).

Sho Tada, Yuki Yamashita, Kohei Matsuda, Makoto Nagata, Kazuo Sakiyama, and Noriyuki Miura, “Design and concept proof of an inductive impulse self-destructor in sense-and-react countermeasure against physical attacks,” J. Appl. Phys. 60, SGGL01, 7pages, (Feb., 2021).

Go Takami, Takeshi Sugawara, Kazuo Sakiyama, and Yang Li, “Mixture-Based 5-Round Physical Attack against AES: Attack Proposal and Noise Evaluation,” IEICE Trans. Fundam. Electron. Commun. Comput. Sci., Vol.E105-A, No.3,, pp.289–299 (Mar., 2021).

Go Takatoi, Takeshi Sugawara, Kazuo Sakiyama, Yuko Hara-Azumi, and Yang Li, “The Limits of Timing Analysis and SEMA on Distinguishing Similar Activation Functions of Embedded Deep Neural Networks,” Appl. Sci. 2022, Vol.12(9), 4135 (Apr., 2022).

Daisuke Fujimoto, Noriyuki Miura, Makoto Nagata, Yuichi Hayashi, Naofumi Homma, Yohei Hori, Toshihiro Katashita, Kazuo Sakiyama, Thanh-Ha Le, Julien Bringer, Pirouz Bazargan-Sabet, Jean-Luc Danger, “On-chip power noise measurements of cryptographic VLSI circuits and interpretation for side-channel analysis,” In Proc. International Symposium on Electromagnetic Compatibility (EMC EUROPE) 2013, IEEE, pp.405–410 (Sep., 2013).