Kazuo Sakiyama, Elke De Mulder, Bart Preneel, and Ingrid Verbauwhede, “Side-channel Resistant System-level Design Flow for Public-key Cryptography,” In Proc. 2007 Great Lakes Symposium on VLSI (GLSVLSI’07), ACM, pp.144–147 (Mar., 2007).
Lejla Batina, Nele Mentens, Kazuo Sakiyama, Bart Preneel, and Ingrid Verbauwhede, “Public-Key Cryptography on the Top of a Needle,” In Proc. IEEE International Symposium on Circuits and Systems (ISCAS’07), Special Session: Novel Cryptographic Architectures for Low-Cost RFID, IEEE, pp.1831–1834 (May, 2007).
Nele Mentens, Kazuo Sakiyama, Lejla Batina, Bart Preneel, and Ingrid Verbauwhede, “A Side-channel Attack Resistant Programmable PKC Coprocessor for Embedded Applications,” In Proc. International Symposium on Systems, Architectures, MOdeling and Simulation (IC-SAMOS’07), IEEE, pp.194–200 (Jul., 2007).
Junfeng Fan, Kazuo Sakiyama, and Ingrid Verbauwhede, “Montgomery Modular Multiplication Algorithm on Multi-Core Systems,” In Proc. IEEE Workshop on Signal Processing Systems (SIPS’07), IEEE, pp.261-266 (Oct., 2007).
Junfeng Fan, Lejla Batina, Kazuo Sakiyama, and Ingrid Verbauwhede, “FPGA Design for Algebraic Tori-Based Public-Key Cryptography,” In Proc. Design, Automation and Test in Europe (DATE’08), ACM, pp.1292–1297 (Mar., 2008).
Miroslav Knežević, Kazuo Sakiyama, Yong Ki Lee, and Ingrid Verbauwhede, “On the High-Throughput Implementation of RIPEMD-160 Hash Algorithm,” In Proc. 19th IEEE International Conference on Application-specific Systems, Architectures and Processor (ASAP’08), IEEE, pp.85–90 (Jul., 2008).
Miroslav Knežević, Kazuo Sakiyama, Junfeng Fan, and Ingrid Verbauwhede, “Modular Multiplication in GF(2n) without Pre-computational Phase,” In Proc. International Workshop on the Arithmetic of Finite Fields (WAIFI’08), LNCS 5130, Springer-Verlag, pp.77–87 (Jul., 2008).
Masami Izumi, Kazuo Sakiyama, and Kazuo Ohta, “A New Approach for Implementing the MPL Method toward Higher SPA Resistance,” In Proc. International Conference on Availability, Reliability and Security (ARES’09), IEEE, pp.181–186 (Mar., 2009).
Kazuo Sakiyama, Tatsuya Yagi, and Kazuo Ohta, “Fault Analysis Attack against an AES Prototype Chip Using RSL,” In Proc. RSA Conference 2009, Cryptographer’s Track (CT-RSA’09), LNCS 5473, Springer-Verlag, pp.429–443 (Apr., 2009).
Daisuke Fujimoto, Noriyuki Miura, Makoto Nagata, Yuichi Hayashi, Naofumi Homma, Yohei Hori, Toshihiro Katashita, Kazuo Sakiyama, Thanh-Ha Le, Julien Bringer, Pirouz Bazargan-Sabet, Jean-Luc Danger, “On-chip power noise measurements of cryptographic VLSI circuits and interpretation for side-channel analysis,” In Proc. International Symposium on Electromagnetic Compatibility (EMC EUROPE) 2013, IEEE, pp.405–410 (Sep., 2013).
