Yang Li, Kazuo Ohta, and Kazuo Sakiyama, “A New Type of Fault-Based Attack: Fault Behavior Analysis,” IEICE Trans. Fundam. Electron. Commun. Comput. Sci., Vol.E96-A, No.1, pp.177–184 (Jan., 2013).
Shugo Mikami, Hirotaka Yoshida, Dai Watanabe, Kazuo Sakiyama, “Correlation Power Analysis and Countermeasure on the Stream Cipher Enocoro-128v2,” IEICE Trans. Fundam. Electron. Commun. Comput. Sci., Vol.96-A, No.3, pp.697–704 (Mar., 2013).
Dai Yamamoto, Kazuo Sakiyama, Mitsugu Iwamoto, Kazuo Ohta, Masahiko Takenaka, and Kouichi Itoh, “Variety Enhancement of PUF Responses Using the Locations of Random Outputting RS Latches,” J. Cryptographic Engineering, Vol.3(4), pp.197–211 (Nov., 2013).
Kazuo Sakiyama, Yang Li, Shigeto Gomisawa, Yu-ichi Hayashi, Mitsugu Iwamoto, Naofumi Homma, Takafumi Aoki, and Kazuo Ohta, “Practical DFA Strategy for AES Under Limited-Access Conditions,” Journal of Information Processing, Vol.22, No.2, 142–151 (Feb., 2014).
Christophe Clavier, Jean-Luc Danger, Guillaume Duc, M. Abdelaziz Elaabid, Benoît Gérard, Sylvain Guilley, Annelie Heuser, Michael Kasper, Yang Li, Victor Lomné, Daisuke Nakatsu, Kazuo Ohta, Kazuo Sakiyama, Laurent Sauvage, Werner Schindler, Marc Stöttinger, Nicolas Veyrat-Charvillon, Matthieu Walle, Antoine Wurcker, “Practical improvements of side-channel attacks on AES: feedback from the 2nd DPA contest,” J. Cryptographic Engineering, Vol.4(1), pp.259–274 (Apr., 2014).
Daisuke Fujimoto, Noriyuki Miura, Makoto Nagata, Yuichi Hayashi, Naofumi Homma, Takafumi Aoki, Yohei Hori, Toshihiro Katashita, Kazuo Sakiyama, Thanh-Ha Le, Julien Bringer, Pirouz Bazargan-Sabet, Shivam Bhasin, and Jean-Luc Danger, “Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage,” IEICE Trans. Electronics, Vol.E97-C, No.4, pp.272–279, (Apr., 2014).
中曽根俊貴, 李陽, 岩本貢, 太田和夫, 崎山一男, “クロック間衝突を漏洩モデルとする新たなサイドチャネル解析と並列実装AES暗号ハードウェアにおける弱い鍵,” 電子情報通信学会論文誌(A), Vol.J97-A, No.11, pp.695–703 (Nov., 2014).
Sho Endo, Yang Li, Naofumi Homma, Kazuo Sakiyama, Kazuo Ohta, Daisuke Fujimoto, Makoto Nagata, Toshihiro Katashita, Jean-Luc Danger, and Takafumi Aoki, “A Silicon-level Countermeasure against Fault Sensitivity Analysis and Its Evaluation,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol.23, No.8, pp.1429–1438 (Aug., 2015).
Dai Yamamoto, Kazuo Sakiyama, Mitsugu Iwamoto, Kazuo Ohta, Masahiko Takenaka, Kouichi Itoh, and Naoya Torii, “A new method for enhancing variety and maintaining reliability of PUF responses and its evaluation on ASICs Journal of Cryptographic Engineering,” J. Cryptographic Engineering, Vol.5(3), pp.187–199 (Sep., 2015).
Takanori Machida, Dai Yamamoto, Mitsugu Iwamoto, and Kazuo Sakiyama, “A New Arbiter PUF for Enhancing Unpredictability on FPGA,” The Scientific World Journal, Hindawi, Vol.2015, Article ID 864812, 13 pages (Aug., 2015).
